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<title>CMSIS-Core (Cortex-M): Revision History of CMSIS-Core (Cortex-M)</title>
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   <div id="projectname">CMSIS-Core (Cortex-M)
   &#160;<span id="projectnumber">Version 5.6.0</span>
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   <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
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<div class="title">Revision History of CMSIS-Core (Cortex-M) </div>  </div>
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<div class="contents">
<div class="textblock"><table  class="cmtable" summary="Revision History">
<tr>
<th>Version </th><th>Description  </th></tr>
<tr>
<td>V5.6.0 </td><td><ul>
<li>
Added: Arm Cortex-M85 cpu support </li>
<li>
Added: Arm China Star-MC1 cpu support </li>
<li>
Updated: system_ARMCM55.c </li>
</ul>
</td></tr>
<tr>
<td>V5.5.0 </td><td><ul>
<li>
Updated GCC LinkerDescription, GCC Assembler startup </li>
<li>
Added ARMv8-M Stack Sealing (to linker, startup) for toolchain ARM, GCC </li>
<li>
Changed C-Startup to default Startup.  Updated Armv8-M Assembler startup to use GAS syntax<br/>
 Note: Updating existing projects may need manual user interaction!  </li>
</ul>
</td></tr>
<tr>
<td>V5.4.0 </td><td><ul>
<li>
Added: Cortex-M55 cpu support </li>
<li>
Enhanced: MVE support for Armv8.1-MML </li>
<li>
Fixed: Device config define checks </li>
<li>
Added: L1 Cache functions for Armv7-M and later </li>
</ul>
</td></tr>
<tr>
<td>V5.3.0 </td><td><ul>
<li>
Added: Provisions for compiler-independent C startup code. </li>
</ul>
</td></tr>
<tr>
<td>V5.2.1 </td><td><ul>
<li>
Fixed: Compilation issue in cmsis_armclang_ltm.h introduced in 5.2.0 </li>
</ul>
</td></tr>
<tr>
<td>V5.2.0 </td><td><ul>
<li>
Added: Cortex-M35P support. </li>
<li>
Added: Cortex-M1 support. </li>
<li>
Added: Armv8.1 architecture support. </li>
<li>
Added: <a class="el" href="group__compiler__conntrol__gr.html#ga378ac21329d33f561f90265eef89f564">__RESTRICT</a> and <a class="el" href="group__compiler__conntrol__gr.html#gab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> compiler control macros. </li>
</ul>
</td></tr>
<tr>
<td>V5.1.2 </td><td><ul>
<li>
Removed using get/set built-ins FPSCR in GCC &gt;= 7.2 due to shortcomings. </li>
<li>
Added __NO_RETURN to __NVIC_SystemReset() to silence compiler warnings. </li>
<li>
Added support for Cortex-M1 (beta). </li>
<li>
Removed usage of register keyword. </li>
<li>
Added defines for EXC_RETURN, FNC_RETURN and integrity signature values. </li>
<li>
Enhanced MPUv7 API with defines for memory access attributes. </li>
</ul>
</td></tr>
<tr>
<td>V5.1.1 </td><td><ul>
<li>
Aligned MSPLIM and PSPLIM access functions along supported compilers. </li>
</ul>
</td></tr>
<tr>
<td>V5.1.0 </td><td><ul>
<li>
Added MPU Functions for ARMv8-M for Cortex-M23/M33. </li>
<li>
Moved __SSAT and __USAT intrinsics to CMSIS-Core. </li>
<li>
Aligned __REV, __REV16 and __REVSH intrinsics along supported compilers. </li>
</ul>
</td></tr>
<tr>
<td>V5.0.2 </td><td><ul>
<li>
Added macros <a class="el" href="group__compiler__conntrol__gr.html#gabe8693a7200e573101551d49a1772fb9">__UNALIGNED_UINT16_READ</a>, <a class="el" href="group__compiler__conntrol__gr.html#gadb9cd73446f7e11e92383cd327a23407">__UNALIGNED_UINT16_WRITE</a>. </li>
<li>
Added macros <a class="el" href="group__compiler__conntrol__gr.html#ga254322c344d954c9f829719a50a88e87">__UNALIGNED_UINT32_READ</a>, <a class="el" href="group__compiler__conntrol__gr.html#gabb2180285c417aa9120a360c51f64b4b">__UNALIGNED_UINT32_WRITE</a>. </li>
<li>
Deprecated macro <a class="el" href="group__compiler__conntrol__gr.html#ga27fd2ec6767ca1ab66d36b5cc0103268">__UNALIGNED_UINT32</a>. </li>
<li>
Changed <a class="el" href="group__version__control__gr.html">Version Control</a> macros to be core agnostic. </li>
<li>
Added <a class="el" href="group__mpu__functions.html">MPU Functions for Armv6-M/v7-M</a> for Cortex-M0+/M3/M4/M7. </li>
</ul>
</td></tr>
<tr>
<td>V5.0.1 </td><td><ul>
<li>
Added: macro <a class="el" href="group__compiler__conntrol__gr.html#ga4dbb70fab85207c27b581ecb6532b314">__PACKED_STRUCT</a>. </li>
<li>
Added: uVisor support. </li>
</ul>
</td></tr>
<tr>
<td>V5.00 </td><td><ul>
<li>
Added: Cortex-M23, Cortex-M33 support. </li>
<li>
Added: macro __SAU_PRESENT with __SAU_REGION_PRESENT. </li>
<li>
Replaced: macro __SAU_PRESENT with __SAU_REGION_PRESENT. </li>
<li>
Reworked: SAU register and functions. </li>
<li>
Added: macro <a class="el" href="group__compiler__conntrol__gr.html#ga0c58caa5a273e2c21924509a45f8b849">__ALIGNED</a>. </li>
<li>
Updated: function <a class="el" href="group__Icache__functions__m7.html#ga980ffe52af778f2535ccc52f25f9a7de">SCB_EnableICache</a>. </li>
<li>
Added: cmsis_compiler.h with compiler specific CMSIS macros, functions, instructions. </li>
<li>
Added: macro <a class="el" href="group__compiler__conntrol__gr.html#gabe8996d3d985ee1529475443cc635bf1">__PACKED</a>. </li>
<li>
Updated: compiler specific include files. </li>
<li>
Updated: core dependant include files. </li>
<li>
Removed: deprecated files core_cmfunc.h, core_cminstr.h, core_cmsimd.h. </li>
</ul>
</td></tr>
<tr>
<td>V5.00<br/>
Beta 6 </td><td><ul>
<li>
Added: SCB_CFSR register bit definitions. </li>
<li>
Added: function <a class="el" href="group__NVIC__gr.html#ga72f102d31af0ee4aa7a6fb7a180840f3">NVIC_GetEnableIRQ</a>. </li>
<li>
Updated: core instruction macros <a class="el" href="group__intrinsic__CPU__gr.html#gac71fad9f0a91980fecafcb450ee0a63e">__NOP</a>, <a class="el" href="group__intrinsic__CPU__gr.html#gaed91dfbf3d7d7b7fba8d912fcbeaad88">__WFI</a>, <a class="el" href="group__intrinsic__CPU__gr.html#gad3efec76c3bfa2b8528ded530386c563">__WFE</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga3c34da7eb16496ae2668a5b95fa441e7">__SEV</a> for toolchain GCC. </li>
</ul>
</td></tr>
<tr>
<td>V5.00<br/>
Beta 5 </td><td><ul>
<li>
Moved: DSP libraries from CMSIS/DSP/Lib to CMSIS/Lib. </li>
<li>
Added: DSP libraries build projects to CMSIS pack. </li>
</ul>
</td></tr>
<tr>
<td>V5.00<br/>
Beta 4 </td><td><ul>
<li>
Updated: ARMv8M device files. </li>
<li>
Corrected: ARMv8MBL interrupts. </li>
<li>
Reworked: NVIC functions. </li>
</ul>
</td></tr>
<tr>
<td>V5.00<br/>
Beta 2 </td><td><ul>
<li>
Changed: ARMv8M SAU regions to 8. </li>
<li>
Changed: moved function <a class="el" href="group__sau__trustzone__functions.html#ga6093bc5939ea8924fbcfdffb8f0553f1">TZ_SAU_Setup</a> to file partition_&lt;device&gt;.h. </li>
<li>
Changed: license under Apache-2.0. </li>
<li>
Added: check if macro is defined before use. </li>
<li>
Corrected: function <a class="el" href="group__Dcache__functions__m7.html#gafe64b44d1a61483a947e44a77a9d3287">SCB_DisableDCache</a>. </li>
<li>
Corrected: macros <a class="el" href="group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e">_VAL2FLD</a>, <a class="el" href="group__peripheral__gr.html#ga139b6e261c981f014f386927ca4a8444">_FLD2VAL</a>. </li>
<li>
Added: NVIC function virtualization with macros <a class="el" href="group__NVIC__gr.html#gadc48b4ed09386aab48fa6b9c96d9034c">CMSIS_NVIC_VIRTUAL</a> and <a class="el" href="group__NVIC__gr.html#gad01d3aa220b50ef141b06c93888b268d">CMSIS_VECTAB_VIRTUAL</a>. </li>
</ul>
</td></tr>
<tr>
<td>V5.00<br/>
Beta 1 </td><td><ul>
<li>
Renamed: cmsis_armcc_V6.h to cmsis_armclang.h. </li>
<li>
Renamed: core_*.h to lower case. </li>
<li>
Added: function <a class="el" href="group__fpu__functions.html#ga6bcad99ce80a0e7e4ddc6f2379081756">SCB_GetFPUType</a> to all CMSIS cores. </li>
<li>
Added: ARMv8-M support. </li>
</ul>
</td></tr>
<tr>
<td>V4.30 </td><td><ul>
<li>
Corrected: DoxyGen function parameter comments. </li>
<li>
Corrected: IAR toolchain: removed for <a class="el" href="group__NVIC__gr.html#ga1b47d17e90b6a03e7bd1ec6a0d549b46">NVIC_SystemReset</a> the attribute(noreturn). </li>
<li>
Corrected: GCC toolchain: suppressed irrelevant compiler warnings. </li>
<li>
Added: Support files for Arm Compiler v6 (cmsis_armcc_v6.h). </li>
</ul>
</td></tr>
<tr>
<td>V4.20 </td><td><ul>
<li>
Corrected: MISRA-C:2004 violations. </li>
<li>
Corrected: predefined macro for TI CCS Compiler. </li>
<li>
Corrected: function <a class="el" href="group__intrinsic__SIMD__gr.html#ga15d8899a173effb8ad8c7268da32b60e">__SHADD16</a> in arm_math.h. </li>
<li>
Updated: cache functions for Cortex-M7. </li>
<li>
Added: macros <a class="el" href="group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e">_VAL2FLD</a>, <a class="el" href="group__peripheral__gr.html#ga139b6e261c981f014f386927ca4a8444">_FLD2VAL</a> to core_*.h. </li>
<li>
Updated: functions <a class="el" href="group__intrinsic__SIMD__gr.html#ga87618799672e1511e33964bc71467eb3">__QASX</a>, <a class="el" href="group__intrinsic__SIMD__gr.html#gab41eb2b17512ab01d476fc9d5bd19520">__QSAX</a>, <a class="el" href="group__intrinsic__SIMD__gr.html#gae0a649035f67627464fd80e7218c89d5">__SHASX</a>, <a class="el" href="group__intrinsic__SIMD__gr.html#gafadbd89c36b5addcf1ca10dd392db3e9">__SHSAX</a>. </li>
<li>
Corrected: potential bug in function <a class="el" href="group__intrinsic__SIMD__gr.html#ga15d8899a173effb8ad8c7268da32b60e">__SHADD16</a>. </li>
</ul>
</td></tr>
<tr>
<td>V4.10 </td><td><ul>
<li>
Corrected: MISRA-C:2004 violations. </li>
<li>
Corrected: intrinsic functions <a class="el" href="group__intrinsic__CPU__gr.html#gacb2a8ca6eae1ba4b31161578b720c199">__DSB</a>, <a class="el" href="group__intrinsic__CPU__gr.html#gab1c9b393641dc2d397b3408fdbe72b96">__DMB</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga93c09b4709394d81977300d5f84950e5">__ISB</a>. </li>
<li>
Corrected: register definitions for ITCMCR register. </li>
<li>
Corrected: register definitions for <a class="el" href="unionCONTROL__Type.html">CONTROL_Type</a> register. </li>
<li>
Added: functions <a class="el" href="group__fpu__functions.html#ga6bcad99ce80a0e7e4ddc6f2379081756">SCB_GetFPUType</a>, <a class="el" href="group__Dcache__functions__m7.html#ga31c2439722ab4dbd0c67b196e3377ca7">SCB_InvalidateDCache_by_Addr</a> to core_cm7.h. </li>
<li>
Added: register definitions for <a class="el" href="unionAPSR__Type.html">APSR_Type</a>, <a class="el" href="unionIPSR__Type.html">IPSR_Type</a>, <a class="el" href="unionxPSR__Type.html">xPSR_Type</a> register. </li>
<li>
Added: <a class="el" href="group__Core__Register__gr.html#ga62fa63d39cf22df348857d5f44ab64d9">__set_BASEPRI_MAX</a> function to core_cmFunc.h. </li>
<li>
Added: intrinsic functions <a class="el" href="group__intrinsic__CPU__gr.html#gad6f9f297f6b91a995ee199fbc796b863">__RBIT</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga90884c591ac5d73d6069334eba9d6c02">__CLZ</a> for Cortex-M0/CortexM0+. </li>
</ul>
</td></tr>
<tr>
<td>V4.00 </td><td><ul>
<li>
Added: Cortex-M7 support. </li>
<li>
Added: intrinsic functions for <a class="el" href="group__intrinsic__CPU__gr.html#gac09134f1bf9c49db07282001afcc9380">__RRX</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga9464d75db32846aa8295c3c3adfacb41">__LDRBT</a>, <a class="el" href="group__intrinsic__CPU__gr.html#gaa762b8bc5634ce38cb14d62a6b2aee32">__LDRHT</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga616504f5da979ba8a073d428d6e8d5c7">__LDRT</a>, <a class="el" href="group__intrinsic__CPU__gr.html#gad41aa59c92c0a165b7f98428d3320cd5">__STRBT</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga2b5d93b8e461755b1072a03df3f1722e">__STRHT</a>, and <a class="el" href="group__intrinsic__CPU__gr.html#ga625bc4ac0b1d50de9bcd13d9f050030e">__STRT</a> </li>
</ul>
</td></tr>
<tr>
<td>V3.40 </td><td><ul>
<li>
Corrected: C++ include guard settings. </li>
</ul>
</td></tr>
<tr>
<td>V3.30 </td><td><ul>
<li>
Added: COSMIC tool chain support. </li>
<li>
Corrected: GCC __SMLALDX instruction intrinsic for Cortex-M4. </li>
<li>
Corrected: GCC __SMLALD instruction intrinsic for Cortex-M4. </li>
<li>
Corrected: GCC/CLang warnings. </li>
</ul>
</td></tr>
<tr>
<td>V3.20 </td><td><ul>
<li>
Added: <a class="el" href="group__intrinsic__CPU__gr.html#ga92f5621626711931da71eaa8bf301af7">__BKPT</a> instruction intrinsic. </li>
<li>
Added: <a class="el" href="group__intrinsic__SIMD__gr.html#gaea60757232f740ec6b09980eebb614ff">__SMMLA</a> instruction intrinsic for Cortex-M4. </li>
<li>
Corrected: <a class="el" href="group__ITM__Debug__gr.html#gaaa7c716331f74d644bf6bf25cd3392d1">ITM_SendChar</a>. </li>
<li>
Corrected: <a class="el" href="group__Core__Register__gr.html#ga0f98dfbd252b89d12564472dbeba9c27">__enable_irq</a>, <a class="el" href="group__Core__Register__gr.html#gaeb8e5f7564a8ea23678fe3c987b04013">__disable_irq</a> and inline assembly for GCC Compiler. </li>
<li>
Corrected: <a class="el" href="group__NVIC__gr.html#gab18fb9f6c5f4c70fdd73047f0f7c8395">NVIC_GetPriority</a> and VTOR_TBLOFF for Cortex-M0/M0+, SC000. </li>
<li>
Corrected: rework of in-line assembly functions to remove potential compiler warnings. </li>
</ul>
</td></tr>
<tr>
<td>V3.01 </td><td><ul>
<li>
Added support for Cortex-M0+ processor. </li>
</ul>
</td></tr>
<tr>
<td>V3.00 </td><td><ul>
<li>
Added support for GNU GCC ARM Embedded Compiler. </li>
<li>
Added function <a class="el" href="group__intrinsic__CPU__gr.html#gaf66beb577bb9d90424c3d1d7f684c024">__ROR</a>. </li>
<li>
Added <a class="el" href="regMap_pg.html">Register Mapping</a> for TPIU, DWT. </li>
<li>
Added support for <a class="el" href="device_h_pg.html#core_config_sect">SC000 and SC300 processors</a>. </li>
<li>
Corrected <a class="el" href="group__ITM__Debug__gr.html#gaaa7c716331f74d644bf6bf25cd3392d1">ITM_SendChar</a> function. </li>
<li>
Corrected the functions <a class="el" href="group__intrinsic__CPU__gr.html#gaab6482d1f59f59e2b6b7efc1af391c99">__STREXB</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga0a354bdf71caa52f081a4a54e84c8d2a">__STREXH</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga335deaaa7991490e1450cb7d1e4c5197">__STREXW</a> for the GNU GCC compiler section. </li>
<li>
Documentation restructured. </li>
</ul>
</td></tr>
<tr>
<td>V2.10 </td><td><ul>
<li>
Updated documentation. </li>
<li>
Updated CMSIS core include files. </li>
<li>
Changed CMSIS/Device folder structure. </li>
<li>
Added support for Cortex-M0, Cortex-M4 w/o FPU to CMSIS DSP library. </li>
<li>
Reworked CMSIS DSP library examples. </li>
</ul>
</td></tr>
<tr>
<td>V2.00 </td><td><ul>
<li>
Added support for Cortex-M4 processor. </li>
</ul>
</td></tr>
<tr>
<td>V1.30 </td><td><ul>
<li>
Reworked Startup Concept. </li>
<li>
Added additional Debug Functionality. </li>
<li>
Changed folder structure. </li>
<li>
Added doxygen comments. </li>
<li>
Added definitions for bit. </li>
</ul>
</td></tr>
<tr>
<td>V1.01 </td><td><ul>
<li>
Added support for Cortex-M0 processor. </li>
</ul>
</td></tr>
<tr>
<td>V1.01 </td><td><ul>
<li>
Added intrinsic functions for <a class="el" href="group__intrinsic__CPU__gr.html#ga9e3ac13d8dcf4331176b624cf6234a7e">__LDREXB</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga9feffc093d6f68b120d592a7a0d45a15">__LDREXH</a>, <a class="el" href="group__intrinsic__CPU__gr.html#gabd78840a0f2464905b7cec791ebc6a4c">__LDREXW</a>, <a class="el" href="group__intrinsic__CPU__gr.html#gaab6482d1f59f59e2b6b7efc1af391c99">__STREXB</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga0a354bdf71caa52f081a4a54e84c8d2a">__STREXH</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga335deaaa7991490e1450cb7d1e4c5197">__STREXW</a>, and <a class="el" href="group__intrinsic__CPU__gr.html#ga354c5ac8870cc3dfb823367af9c4b412">__CLREX</a> </li>
</ul>
</td></tr>
<tr>
<td>V1.00 </td><td><ul>
<li>
Initial Release for Cortex-M3 processor. </li>
</ul>
</td></tr>
</table>
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